PIN ASSIGNMENT
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LOGIC DIAGRAM
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TRUTH TABLE
OPERATING MODE |
INPUTS |
OUTPUTS |
![](sdinv.gif) |
![](rdinv.gif) |
CP |
D |
![](q2.gif) |
![](q2inv.gif) |
Asyn. Set
Asyn. Reset (Clear)
Undetermined![](ar.gif)
Load "1" (Set)
Load "0" (Reset)
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L H L H H
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H L L H H
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X X X
![](rise.gif)
![](rise.gif)
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X X X h l
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H L H H L
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L H L L H
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H = HIGH voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level steady state.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = don't care.
= LOW-to-HIGH clock transition.
NOTE
Both outputs will be HIGH while both and are LOW.
But the output states are unpredictable if and go HIGH simultaneously.
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